ASML FPGA designer in Veldhoven, Netherlands
Are you challenged by the digital Hardware embedded in the ASML Products? Do you have a Bachelor or Masters Degree in Computer Sciences, Electrical Engineeringe or equivalent and Experience in the design of FPGA's systems? We might be looking for you.
As an FPGA Designer, your mission is to define, realize, manage and maintain the realization of FPGA designs that belong to ASML's company-internal IP block library. This library is used to create and maintain electronics that is embedded in the ASML products.
The FPGA Designer is responsible for the following:
- Participate as an FPGA designer and expert in an Electronics-oriented design team.
- Define and document requirements for the IP blocks in ASML's IP Block Library.
- Contribute to the further development of the IP library by personally developing and maintaining IP blocks (i.e. coding).
- Define, document and execute tests to ensure tha the developed IP Blocks satisfy the requirements.
- Solve IP-block related problems and/or manage problem resolution during integration.
Bachelor or Masters Degree in Electrical Engineering, Computer Sciences or equivalent.
- Experiences in the design of programmable logic (experience in the use of the VHDL design language is a strong plus).
- Technical knowledge of Programmable Logic but also of digital design in general.
- High motivated team player with good social and communication skills.
- Ability to convince others of certain design choices based on arguments.
- Accurate, systematic approach, analytical, problem solving.
- Takes ownership in case of issues.
- Fluent English in word and writing (Dutch is convenient but not mandatory)
Context of the position
The sector Development & Engineering (D&E;) of ASML is responsible for the specification, design anr realization of the products in the ASML portfolio.
Within the sector D&E; the department Electronic Development (EDEV) is responsible for the definition, realization, qualification and integration of all electronic functions and modules within these products.
Within EDEV the group System Electrical Architecture (SEA) is responsible for the architecture, design, realization and qualification of electrical functions that are relevant for the system as a whole (i.e. not only for a particular subsystem of component). Withing the scope of the SEA group the EGD team is responsible for the maintenance of ASML's IP library.
The FPGA Designer will report to the Team Lead of the EGD team.
Be advised that this concerns a flex opportunity with an option to become a regular ASML employee after 12 months. All contracting (payroll) will be handled by ASML’s preferred third party vendor, in accordance with ASML’s remuneration package. Please take this into consideration when you apply for this vacancy
Please add your complete & recent CV and cover letter for this position to your application. We can't process your application without the above mentioned documents.
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Location: Veldhoven, Netherlands
Experience: 2-5 Professional
Available since: 2017-08-10
Functional area: Research & Development
Background: Electronics, Mechatronics, Others - Technical