ASML Metrology Grid and SPM Metrology Design Engineer in Veldhoven, Netherlands


Do you have a MSc, PDEng or PhD in engineering? Do you have experience with Matlab, Mathematica or Maple? Would you like to become our next Metrology Grid & SPM Design Engineer? Then please continue to read because this might be your next adventure!

Job Mission

As a part of ASML’s Metrology team, you will develop, realize and qualify mathematical solutions that are gating for the nanometer performance of our lithographic machines and enable the extension of the roadmap of the lithographic industry (Moore’s law).

Job Description

Metrology software solutions incorporate system design aspects that cover the spectrum from development, realization, integration, manufacturing, installation, to support. A metrology design engineer is responsible for designing

To advance our metrology competence is another aspect of the work. This way we stay on top of what’s required to assure the timely delivery of state of the art solutions for ASML’s product roadmap.


MSc, PDEng or PhD in engineering (physics, mathematics, mechanical, electrical).


Experience with Matlab, Mathematica, Maple, or similar packages is required. Experience in a technical product development environment is a pre. Knowledge about the SW development process and tools is also beneficial

Personal skills

We expect you to be a good communicator, team player, self-starter, to take initiative and to be result oriented.

Context of the position

Sector Information

The DE DUV sector is internally responsible for the specification and development of ASML DUV products. The Wafer Table and SPM department is responsible for developing of a wafer positioning system that is needed for accurate projection of the ic-design layer onto a wafer. The department is divided into multiple groups each of which works in its own specialist subsystem / area.

Position in the Organization

The holder of this position reports to the Group Leader Grid & SPM Metrology and operates within a multidisciplinary development project team.

This position is within the DUV D&E; Department – SPM & Wafer Table, which is responsible for the positioning of the wafer and reticle in ASML’s wafer scanners and for the measurements, models and calibrations which are required for optimal positioning.

Other Information

Keywords: Mathematics, Physics, Electronics, Mathematics, MATLAB, Mathematica, Maple, Unix/Linux, engineer, design engineer, integration, electrical engineering, lithography.

Location: Veldhoven, Netherlands

Level: Master

Experience: 2-5 Professional

Available since: 2017-07-03

Background: Physics, Software Engineering, Mechatronics, Mathematics

Reference: RC06297